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  Title	ASML is entering a 10-year virtuous cycle driven by skyrocketing chip complexity. Market underestimates industry outperformance potential. Could you provide feedback on my growth thesis?
  Children	Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots Comment by WaIlstreetBots
  ID	29138506
  External ID	1php7if
  Author	CommonScientist4447
  Published Date	Dec. 8, 2025, 3:39 p.m.
  Summary	I recently studied ASML and I was astounded by how strong the growth story is. Although ASML’s moat is widely acknowledged by investors, the growth story for the next ten years is highly misunderstood
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  URL	https://www.reddit.com/r/ValueInvesting/comments/1php7if/asml_is_entering_a_10year_virtuous_cycle_driven/
  Sentiment	Negative: 0.01244    Neutral: 0.71091    Positive: 0.27665
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  Content ID	36735703
  Key	bc093df5-0a07-49cd-ae58-bf232ae06a6d
  Content	I recently studied ASML and I was astounded by how strong the growth story is. Although ASML’s moat is widely acknowledged by investors, the growth story for the next ten years is highly misunderstood and constrained to buzzwords such as “AI.” The true drivers of ASML’s growth aren’t simply “more chips required for AI,” but something far more structural, predictable, and exponential. I would love some feedback from the community. For those interested, my full article is here: [https://substack.com/home/post/p-180653543](https://substack.com/home/post/p-180653543) *The Growth Driver* The deepest insight behind ASML’s growth comes from inverting the question. Instead of asking, “How many machines will ASML sell?”, you ask, “How many machines do chipmakers *need* to buy?” That inversion works like magic because it reframes the entire business: a customer doesn’t buy ASML machines, they buy **wafer passes**. Modern chips have over 50-70 layers, and every single layer requires a pass through a lithography scanner. Crucially, as features shrink, a single layer often demands multiple passes (double-,triple-, or quadruple-patterning) just to define the wires/transistors. Each pass involves nearly all five steps (i.e. lithography, etching, etc.) we outlined above, and thus, the more passes through the factory, the more expensive and delayed a chip is. For that reason, chip manufacturers optimize their production lines to minimize wafer passes for the number of target perfect chips. From ASML’s standpoint, because machines have a fixed throughput, the more wafer passes the chip industry needs, the more machines they will have to buy. The core argument for ASML is that **wafer passes are about to start increasing exponentially due to increased chip complexity**, and thus, ASML will outpace industry volumes**.** The actual equation to visualize wafer pass economics is:  wafer passes = chip volume \* layers per chip \* passes per layer Each term in that equation is accelerating—simultaneously. Finally, ASML doesn’t just benefit from more passes—it benefits from each pass becoming more valuable as it sells more machines with higher ASP than in the past. The complete growth equation is: **ASML Revenue = Wafer Passes × Revenue Per Pass** Let’s break down each multiplier. # Chip Volumes Slayed to Increase *Volume Driver #1: More Advanced Chips* The key insight: AI requires significantly more advanced chips which in turn require more advanced lithography machinery. This is the most intuitive growth driver. Structural forces such as AI, robotics, autonomous vehicles, and edge devices (PCs, smartphones, EV) require chips that have ever increasingly smaller features (transistors/cables) due to high computational demand. As a result, new fabs are redesigning to include a higher number of EUV and High NA machines because DUV machines are physically not capable of delivering on the advanced chips that are required. Chief among the growth vectors is AI. What’s critical to observe is that we are extremely early on AI and what will accelerate adoption is increased competition to NVIDIA and the layering of AI across business/consumer applications. As more players start/continue to enter the AI chip market, the exorbitant prices NVIDIA charges must come down, which will exponentially decrease the cost of AI, and thus adoption will skyrocket over the next 10 years. This sets chip volumes to increase even more requiring an ever increasing number of advanced lithography machines by ASML. *Volume #2: Memory Transitions to EUV* The key insight: memory chips are moving to EUV finally. Broadly speaking, there are two types of chips, logic and memory chips. Up until recently, memory chip manufacturers (SK Hynix, Micron) were using only DUV machines due to the prohibitive cost of EUV. Nevertheless, as they pushed miniaturization to limits with their DUV machines, they hit a physics wall that forced them to finally adopt EUV. This is a colossal moment for ASML, because memory manufacturers represent 40% of semiconductor capital spending. *Volume #3: Geopolitical Sovereignty* The key insight: governments are helping to build out domestic fabs due to strategic national security concerns. Governments worldwide have decided that semiconductor manufacturing is a national security imperative. The U.S. CHIPS Act, EU Chips Act, Japan’s semiconductor subsidies, and programs in Korea, India, and Taiwan collectively represent over $200 billion in committed government support for fab construction. This is driving a multi-year construction supercycle independent of end-market demand. These fabs are getting built whether or not smartphone sales grow, because the objective is strategic domestic capacity. And crucially, many of these are leading-edge fabs (to justify the subsidy investment), which means high ASML content per facility. Sovereign demand introduces inefficiency in the fab market because the build out is not based on end-market demand, but rather on government strategic priorities. Nevertheless, it’s an increasing trend And ASML should be a beneficiary over the next 10 years. *Volume #4: Memory and Logic Stacking (3D Chips)* The key insight: even if the number of final products (iPhones, laptops, servers) stays flat, 3D stacking multiply the number of chips that must be made. Traditionally, a chip is flat—think of it like a single-story building. But manufacturers are now stacking multiple chips on top of each other like floors in a skyscraper. This 3D approach solves a critical problem: you can pack more capability into the same footprint and move data between chips much faster. High-bandwidth memory (HBM)—the memory used in AI chips—is the clearest example. Instead of one memory chip, you stack 8-12 identical memory chips vertically and connect them with microscopic vertical tunnels. Here’s the catch: each of those 8-12 chips still needs to be manufactured individually using ASML’s machines**.** Where you previously made one memory chip, you now make twelve. Same end product, but 12x the lithography demand. # Layers Per Chip Drive More Lithography *Layers #1: Shrinking Features Require More Layers* The key insight: every advancement in chip technology—whether moving to a newer node (node = generation, and the smaller the number the more advanced it is, i.e. 7nm —> 5nm —> 2nm) or adding new features like extra memory—translates directly into more physical layers, which means more passes through ASML’s lithography machines. The entire industry is getting more complex, and complexity equals more ASML equipment. Here’s a counterintuitive truth: as chip features get smaller, the chips themselves require more layers to build. It’s like saying that as you make bricks tinier, you need more floors to build the same house. Why does this happen? Because shrinking features demands more architectural sophistication. Think of it like engineering: a small sports car needs more complex suspension, more precise manufacturing, and more parts than a simple go-kart, even though it’s trying to do fundamentally the same thing (move forward). The result: a chip made at 7nm might have 50-60 physical layers. Move to 3nm, and you’re suddenly at 70-80 layers. That’s 30-40% more lithography passes for ASML’s machines. And this complexity isn’t limited to cutting-edge chips. As older process nodes mature and become cheaper to manufacture, products migrate down from 28nm to 16nm or from 40nm to 22nm to save costs. When they make that jump, they inherit 20-30 additional layers that come with the more advanced process. A chip design that needed 35 lithography passes at 28nm suddenly needs 55-60 passes at 16nm. *Layers #2: Gate-All-Around Transistors* The key insight: The semiconductor industry is switching to a fundamentally new transistor design that requires 50% more lithography steps to manufacture. This transition is inevitable, already happening, and will affect every advanced chip made over the next decade. Transistor technology is inevitably transitioning from “FinFET” to “Gate-All-Around” transistors. Although this is highly technical, what it simply means is that GAA transistors are much harder to build. An old FinFET transistor requires about 15-20 lithography passes to manufacture. A GAA transistor requires 25-30 passes—that’s 50% more. *Layers #3: Backside Power Delivery* The key insight: chip manufacturers are starting to print 10-15 layers of certain functionality in the back of the wafer, freeing up 10-15 layers on the front side for more advanced layers. Backside power delivery represent another architectural inflection point. Simply, up until recently, manufacturers were printing on one side of the wafer. With backside power delivery, they print 10-15 layers of certain functionality on the back of the wafer because it makes the chip significantly more efficient. In turn, this frees up more layers for the upfront side to add. Backside power is a one-way door. Once chipmakers qualify it for a chip generation, it becomes standard for all subsequent nodes because the performance and power benefits are too significant to abandon. This is 10-15 permanent additional layers added to every advanced chip going forward. *Layers #4: Energy Efficiency Requirements* The key insight: The push for energy efficiency doesn’t reduce layers—it increases them. Every percentage point of power savings requires additional architectural sophistication, which translates directly into more lithography steps. You might think that making chips more energy-efficient would make them simpler—but it actually does the opposite. Every time a chip is redesigned to use less power, it usually needs more tiny steps to get there. Data centers are huge power hogs. AI supercomputers can suck up 50–100 megawatts—roughly the output of a small town. Companies are now limited not just by money, but by how much electricity they can use. To make chips that use less energy, manufacturers move to smaller, more advanced designs. But smaller designs mean more layers in the chip, and each layer needs multiple passes through ASML’s machines. On top of that, advanced chips need extra circuitry to control power and distribute electricity efficiently. Each of these features adds even more layers. # Passes Per Layer Increases *Passes #1: Fields Per Chip* The key insight: Bigger chips and smaller machine “paintbrushes” mean more passes for ASML machines. Every chip has to be exposed in sections, and as chips get bigger or the machine’s field gets smaller, the number of passes per chip multiplies. Here’s what that means in practice: A lithography machine can only print a certain area of the wafer at a time, called a “field.” For small chips, you can fit many of them in one field per layer, so one pass is enough. But as chips get bigger, they need multiple fields per chip. Modern GPUs are massive. Nvidia’s H100, for example, is almost as big as the maximum exposure area of a standard EUV machine. That means each layer needs 2 passes instead of 1. AMD’s MI300 is even larger. High NA machines make this more extreme. Their field size is smaller—about half of standard EUV. That same GPU now needs 3–4 passes per layer instead of 2. The result: Every large chip now requires 2–4x more passes through the lithography machine. And chips aren’t shrinking—AI processors, server CPUs, and high-end GPUs keep getting bigger to pack in more compute. Bottom line: Bigger chips plus smaller fields create a multiplier effect, dramatically increasing the number of passes per chip. *Passes #2: Stitching Complexity* The key insight: When chips are bigger than the machine’s “paintbrush,” the sections must be stitched together perfectly, which slows everything down and forces customers to buy more machines. Here’s the story: A lithography machine can only expose a certain area at a time, called a “field.” If a chip is larger than that field, the machine has to expose multiple fields and then carefully align them to create one complete layer. This process is called stitching. Stitching isn’t just putting pieces together. Each overlap requires extreme precision—down to a few nanometers. This extra work slows down the machine because it can’t just fire and move on; it must check and adjust constantly. The effect on fabs is simple but powerful: slower throughput per machine means chipmakers need more machines to hit their production targets, even if the machine’s rated “wafers per hour” hasn’t changed. Stitching large chips creates a hidden multiplier on machine demand. More complex chips + nanometer-precise stitching = more passes, more time, and ultimately more ASML machines needed. *Passes #3: Chiplets* The key insight: Breaking a big chip into smaller chiplets actually increases the total work for lithography, because each smaller piece still needs to go through the full process, plus there’s extra work to connect them. Instead of making one large chip, modern designs often use 3–5 smaller chiplets. Each chiplet must go through all the lithography steps independently. On top of that, you need an “interposer” or base layer to connect the chiplets together. Even though interposers usually use DUV instead of EUV, this still adds significant incremental demand for lithography that didn’t exist when chips were made as a single, monolithic piece. *Passes #4: Advanced Packaging* The key insight: The “box” the chip comes in used to be dumb plastic; now it is smart silicon. Historically, ASML’s job ended once the chip was finished. But today, chips are being broken into smaller pieces and stacked on top of each other like Lego bricks. To make these stacked chips talk to each other, manufacturers have to print millions of tiny connections *outside* the main chip. This transforms “packaging” from a low-tech plastic molding step into a high-tech lithography step—giving ASML a second bite at the apple on every device sold. # Higher Revenue Per Pass: The ASP Escalator ASML’s revenue doesn’t just scale with the number of passes—it scales with the value of each pass. As the mix shifts from DUV to EUV to High NA, ASML captures exponentially more revenue per wafer processed. *Higher ASP #1: Single-Pass Patterning* The key insight: ASML sells the world’s most expensive “delete” button. When a customer pays $380 million for a High-NA machine, they aren’t paying for “more” manufacturing; they are paying for *less*. They are buying the ability to delete 3 or 4 redundant loops of manufacturing steps. This creates a paradox: the most expensive machine on the market is actually the cheapest way to build a chip. To understand why ASML can charge double the price for its new machines, you have to understand the nightmare of the alternative. Imagine you are trying to project a highly detailed image onto a wall, but your projector is blurry (the old DUV machine). To get a sharp image, you can’t just project it once. You have to use a “trick”: you project the left edge, then the right edge, then the top, then the bottom, overlapping them perfectly to create the final picture. In the chip world, this is called multi-patterning. To print one layer of a chip using older machines, the factory has to run the wafer through the entire assembly line 3 or 4 times. That means 3x the electricity, 3x the chemicals, and 3x the chances to accidentally break the wafer. High-NA is the 4K Projector. The new High-NA machine is so sharp that it can print that complex image in one single shot. This transforms the economics of the factory: * Old Way: Buy a cheaper $150M machine, but pay to run the factory loop 4 times. * New Way: Buy the expensive $380M machine, but run the factory loop only once. This is why ASML has pricing power. They know that even at $380 million, their machine is still the customer’s cheapest option because it eliminates the massive operational costs of those extra steps. ASML simply captures a portion of the money they save the customer. *Higher ASP #2: Value-Based Pricing* The key insight: ASML can charge such a higher price for new machines (i.e. EUV, High NA) because on a per chip basis, it is cheaper for the customer than older generation machines. ASML doesn’t price based on manufacturing cost—it prices based on customer value delivered. This is especially pronounced for EUV and High NA, where ASML is the sole supplier and customers have no negotiating leverage. When TSMC adopts High NA and achieves 1.7x transistor density improvement, that translates into billions of dollars in additional revenue from customers (Apple, Nvidia, AMD) willing to pay premium prices for cutting-edge chips. ASML captures a portion of that value through its pricing. *Higher ASP #3: Yield Improvements and Customer Economics* The key insight: Better lithography doesn’t just make chips smaller—it improves yield, which makes expensive machines worth it. EUV and High NA reduce errors during manufacturing. They create sharper patterns, smoother edges, and fewer defects on each wafer. This means more chips actually work—what engineers call higher yield. Higher yields directly improve a chipmaker’s return on investment. If one wafer now produces 5–10% more usable chips, spending more on a High NA machine suddenly makes perfect sense. The chipmaker gets more good chips without needing more wafers. # Share of Fab Capex Expansion Lithography is capturing a larger percentage of total fab equipment spending. Historically, lithography represented 20-25% of fab capex. Today, for leading-edge fabs, it’s approaching 30-35%. This isn’t because other equipment categories are shrinking—it’s because single-pass lithography eliminates the need for redundant equipment. Multi-patterning required extra etchers, deposition tools, and metrology systems to support the additional process steps. EUV and High NA eliminate those steps, and the capital budget reallocates to lithography. # The Compounding Effect The main point of the exponential growth in volumes/layers/passes is that ASML revenues will outpace industry volumes because machine purchasing decisions are based on wafer passes, which will skyrocket over the next decade. The key insight is that these multipliers don’t just add—they compound: * **AI drives fab construction** → **new fabs target advanced nodes** → **advanced nodes need EUV/High NA** * **More layers per chip** → **DUV can’t handle the complexity** → **layers migrate to EUV** → **EUV enables even more complexity** * **Chips get larger** → **fields per chip increases** → **more passes required** → **more machines needed per fab** * **High NA eliminates multi-patterning** → **chipmakers consolidate spending on ASML** → **ASML captures larger share of fab capex** → **more R&D for Hyper NA** → **cycle extends** This is a flywheel, not a linear trend. ASML isn’t riding industry growth—it’s growing faster than the industry at every level of the stack. The company is capturing an ever-increasing share of semiconductor value creation because lithography is becoming more critical, more complex, and more irreplaceable with each generation. For the next decade, those fundamentals point in one direction: **more machines per fab, more expensive machines per fab, and more value captured per wafer processed.**
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